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| !""# $!%!! &'( !""# %!) description signal address input a0~a18 data input/output d0~d31 chip select /cs1~4 write enable /we output enable /oe no connect nc power v cc ground v ss ! ! "" # $% & ' # '( )%'* # + , &-. , ,/ 0, .,, # 11+ , $ 0, # -. ,/ ,0 . # /2 , %" & % # + 0 /3 40, ! "#$ $# "!*+!!" 56 , $ 7 0, 7 6 6 / .,$ . . ,/ , ,/ . 86 6 / 7 , . ,/ 6 . 39& 1194 : 6567 , $$, $ .0, 0 6 /2. , $ ., % , " 2 8 563" ''';< %" 39 . 6 . 0 86 6 0 8 6 611+++ , $% & ' , , 7 2 56 '(7 7 2 , . , 0, .,, 560 , ,. . 6 % =39 <> &8 6$ .,$ 6 0 $ 6 . $ ., 62 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram d0~7 d8~15 d16~23 d24~31 d0~7 d8~15 d16~23 d24~31 cs1 cs2 cs4 cs3 a0~18 /oe /we ! pin signal pin signal 1 vcc 35 vcc 2 nc 36 a13 3 /cs1 37 a12 4 /cs2 38 a11 5 /cs3 39 a10 6 /cs4 40 a9 7 a17 41 a8 8 a18 42 a7 9 d16 43 d0 10 d17 44 d1 11 d18 45 d2 12 d19 46 d3 13 gnd 47 gnd 14 d20 48 d4 15 d21 49 d5 16 d22 50 d6 17 d23 51 d7 18 vcc 52 vcc 19 d24 53 d8 20 d25 54 d9 21 d26 55 d10 22 d27 56 d11 23 gnd 57 gnd 24 d28 58 d12 25 d29 59 d13 26 d30 60 d14 27 d31 61 d15 28 a6 62 a14 29 a5 63 a15 30 a4 64 a16 31 a3 65 /we 32 a2 66 /oe 33 a1 67 nc 34 a0 68 nc parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.2 - v cc +0.5 v input low voltage v il (1) -0.5 - 0.8 v operating temperature t a 0 - 70 o c t ai -40 - 85 o c (i suffix) % &' ' (()* ( *+ *, param eter symbol min max unit voltage on any pin relative to v ss v t -0.5 to v cc +0.5 v voltage on v cc relative to v ss v t -0.5 to 7.0 v power dissipation p t 5.3 w storage temperature t stg -55 to +125 o c ! "# ! $"% $# & # ' ( ) parameter symbol test condition min typ max unit input leakage current i li v in = 0v to v cc -16 - 16 a output leakage current i lo v i/o = 0v to v cc -16 - 16 a operating supply current (2) 32 bit i cc32 /cs (1) =v il , i i/o =0ma,f=f max , - - 980 ma min. cycle, v in = v ih or v il 16 bit i cc16 as above. - - 730 ma standby supply current i sb /cs (1) =v ih ,min cycle - - 480 ma i sb1 f=0mhz, /cs> vcc-0.2v, 120 ma v in > vcc-0.2v or v in < 0.2v output voltage low v ol i ol =8.0ma - - 0.4 v output voltage high v oh i oh =-4.0ma 2.4 - - v 166? 30pf i/o pin 1.76v * parameter symbol test condition min typ max unit input capacitance, address, /oe, /we c in1 v in = 0v - - 64 pf output capacitance, 16 bit mode (worst case) c i/o v i/o = 0v - - 40 pf - * ( ). ( # -0. 0. 7 ?'( "'( # -0. , $ ?" # -0. 4. 0. ,$, 7 ?% ( # 4. 0. ?3 , #( @ '( )%'* # . " 2 * /cs1 /cs2 /cs3 /cs4 /oe /we supply current mode l h h h x l i cc16 write d0~d15 h l h h x l i cc16 write d16~d31 h h l h x l i cc16 write d0~d15 h h h l x l i cc16 write d16~d31 l l h h x l i cc32 write d0~d31 h h l l x l i cc32 write d0~d31 l h h h l h i cc16 read d0~d15 h l h h l h i cc16 read d16~d31 h h l h l h i cc16 read d0~d15 h h h l l h i cc16 read d16~d31 l l h h l h i cc32 read d0~d31 h h l l l h i cc32 read d0~d31 x x x x h h i cc32 /i cc16 d0~d31 high-z h h h h x x i sb , i sb1 d0~d31 standby ) -,-% +(, -(,. /(, , '(*/ 0*/ 15 20 25 parameter symbol min max min max min max units read cycle time t rc 15 - 20 - 25 - ns address access time t aa - 15 - 20 - 25 ns chip select access time t acs - 15 - 20 - 25 ns output enable to output valid t oe - 7 - 9 - 11 ns output hold from address change t oh 3 - 3 - 3 - ns chip selection to output in low z t clz 3 - 3 - 3 - ns output enable to output in low z t olz 0 - 0 - 0 - ns chip deselection to output in high z t chz 0 7 0 9 0 11 ns output disable to output in high z t ohz 0 7 0 9 0 11 ns 15 20 25 parameter symbol min max min max min max units write cycle time t wc 15 - 20 - 25 - ns chip selection to end of write t cw 12 - 14 - 16 - ns address valid to end of write t aw 12 - 14 - 16 - ns address setup time t as 0 - 0 - 0 - ns write pulse width (/oe high) t wp 12 - 14 - 16 - ns write recovery time t wr 0 - 0 - 0 - ns write to output in high z t whz 0 7 0 9 0 11 ns data to write time overlap t dw 8 - 10 - 12 - ns data hold time from write time t dh 0 - 0 - 0 - ns output active from end of write t ow 3 - 3 - 3 - ns address data out valid data t rc t aa t acs t olz t clz(4,5) t chz(3,4,5) t ohz t oh /cs /oe notes (read cycle) 1. /we is high for read cycle. 2. all read cycle timing is referenced from the last valid address to the first transition address. 3. t chz and t ohz are defined as the time at which the outputs achieve the open circuit condition and are not referenced to v oh or v ol levels. 4. at any given temperature and voltage condition, t chz (max.) is less than t clz (min.) both for a given device and from device to device. 5. transition is measured 200mv from steady state voltage with load(b). this parameter is sampled and not 100% tested. 6. device is continuously selected with /cs=v il . 7. address valid prior to coincident with /cs transition low. 8. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 9. /cs=/cs1~4 t oe previous data valid data valid address data out t rc t aa t oh '(*/ " ! "# $# '(*/ $# valid data address /oe /cs data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t dw t dh t ohz(6) high z high z(8) /we notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite p hase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. 11 ./cs=/cs1~4 0*/ " "# %& 0*/ "# '( )* /cs address data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t whz(6) high z high z(8) /we valid data t dw t dh t ow (10) (9) notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite p hase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. 11 ./cs=/cs1~4 0*/ ! /cs address data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t whz(6) high z high z(8) /we valid data t dw t dh t lz high z high z notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if /oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. 11 /cs=/cs1~4 1++* .** 25.02 (0.985) sq. 25.27 (0.995) sq. 1.27 typ. 0.46 typ. 0.10 (0.004) (0.210) max 5.33 24.13 (0.950) 23.11 (0.910) 0.90 (0.035) typ. (0.050) (0.018) pin 1 pin 68 " ) + , -./) ! " ! ##$ %&$' %#% % $ % % %% % %#$ % ( $$ % &'$# % ! $& %&$ ) $ # $)$) *$)$ # $!+# #% %)$#& " )'%, ' !# % ( % # $ # $ % $ &$ #$ # #')%% % & ))$ " # ( -)$ ($ % ))$" & #') % $#$ ## . '/% / % / % .')$ $0 %1/ 2''$# / % $ 2%$# % 0/ 23 ! 4 $ 5/2') % *$ % % / 60 76- $ 6-8 .# % 3/ 396::## #1 ;6/ <22 2 3 (( 7 0 a3-b35''%<+ , 4/ 7 , , 36 $ $ 3 < % 6 cd' + ce'*, 76. / 9f $ , 6 2 6 2 0&7 6 8 2 .2g $, ,,$ 8&7 0 .,06 ,$ 8& , h. 7 0, 0 0 2 / 0 ' + - ? ? . 8 6 ! f ., $ ,/ $c"' +b'*9f . <?3 , c '*9f -$ 6 , , , , i '*86, " +)b *7 / -0 0 $ 2 8 -$2 ,h. ,&7 /22 $ ,? ? d6 ., % +)b *$ ,6 6 0, .,7 , . <?%e 6 ., d' +) +b' + c *9f$ , 8 0, .,7 , (( 7 0 ,/ , &135' ' , / , 5 0 , 7 2 $ , 6 0 h. ''0 .0 ,h. (' ( -9b+ 7 9 09 +b 50 %" + % ' 50, ., + 5 8 6 + $0 ' 9 0 8 +b ( 0 .,6 9 0.0, +b 50, ., % %e + 5 8 6 + $0 ' 9 0 8 +b 0 1 1 |
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